Design and Layout of a 4th Order MASH Architecture ΣΔ- Modulator in 180nm Technology

The interface between the analog world and digital systems requires data converters. To lower the quantization noise level in the signal band, Sigma-Delta(ΣΔ) Analog to Digital Converters (ADCs) employ oversampling and noise shaping approaches. The operation of oversampling is performed by the modulator. Quantization noise and input signal are separated into two distinct frequency bands using two different transfer functions. Digital processing is used to filter the noise from the output signal (sample sequence). In this paper, we investigate the construction and implementation of 4th order cascaded (2–2) Multistage noise Shaping-MASH architectural modulator. The 4th order modulator is designed and verified in UMC 180nm technology with VDD = 3.3V, VREF = 1.2V, VCM = 1V, IREF = 10µA and clock frequency of 32MHz and occupies the active area of 218mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.