A Novel Methodology of Automated Test Promotion Flow for SOC Verification

Current trends in Very Large-Scale Integrated circuits (VLSI) design and verification involve complex systems where testing and validation of chips are expected to be robust and reliable. System-On-Chips (SOCs) involve integration of multiple Intellectual Property systems (IPs) alongside bus interfaces, pads and pins which must fulfil the sign-off criteria in-terms of test specifications and requirements. Therefore, there is a need to improve efficiency pertaining to time consumption, effort estimation and resource management. In-order to achieve these goals, functional verification of test vectors is essential for both pre-silicon and post-silicon sign-off. This is made tangible via promotion of tests from IP level to SOC level, consequently verifying the functional correctness and delivering the tests to test engineering team. The process involves manual efforts and challenges at various levels until test delivery, thus involving substantial consumption of manual efforts and time duration for iterative tasks. In-order to overcome these overheads, a novel methodology for automated way of flow has been proposed where tests are collected, promoted, simulated, and dumped with log files and waveform database. The flow mitigates the issues associated with manual errors, tasks, and implementation. This paper discusses about the methodology, implementation, advantages, and applications of the automated test promotion flow for functional verification of SOCs.