RISC-V Architecture based Hardware Accelerator for kNN

The demand for smarter devices has pushed embedded systems to their limits, particularly in computationally intensive tasks like image recognition and natural language processing. Hardware accelerators have emerged as a solution, offering significant performance and energy efficiency gains. However, traditional accelerators tied to specific processor architectures suffer from limitations like reduced flexibility and vendor lock-in. This project proposes a hardware accelerator for the K-Nearest Neighbor (kNN) algorithm, leveraging the open-source RISC-V architecture. RISC-V addresses the computational complexity, performance bottlenecks, and energy efficiency challenges of existing kNN implementations. The accelerator is designed with key features such as a customized instruction set, parallelism, pipelining, reduced power consumption, and optimized area utilization. The project aims for efficient use of flip-flops (FFs) and look-up tables (LUTs), ensuring optimal resource utilization.By utilizing RISC-V's flexibility, this project aims to create an efficient hardware accelerator for kNN, enabling real-time processing of large datasets, minimizing energy use, and ensuring scalability across different applications.