Performance Evaluation of Adder Topologies Integrated into MAC Units and MLP Model for Digit Recognition

Multilayer perceptron (MLP) is a variant of deep neural networks often used in handwritten digit classification and recognition. Conventional processors, such as CPUs and GPUs, encounter computational challenges with the increasing complexity of MLP models, and ASIC development is time-consuming. This work aims to enhance MLP prediction algorithms using FPGA-based Multiply and Accumulate (MAC) arrays. FPGAs offer a promising alternative due to their flexibility and hardware acceleration potential. An RTL was designed using Verilog HDL in Xilinx Vivado to perform MAC operations for the MLP module with a multiple processing element (PE) MAC array, synthesized on the ZCU-104 FPGA. Various adder topologies including ripple carry adder (RCA), carry select adder (CSelA), and carry look-ahead adder (CLA), were incorporated into the PEs. The MLP model, trained and tested on the MNIST dataset, achieves an accuracy of 97.6%. The 64 PE model can classify 10,100 images per second with 96.5% accuracy using 32-bit fixed-point numbers. The CSelA-based MAC array demonstrates a 32.33% reduction in computational delay compared to RCA, making it ideal for high-speed hardware accelerators.