Analyzing Multilayer Graphene Nanoribbon‐Based Via‐Interconnect Scheme: Prospects and Challenges for Monolithic 3D Integrated Circuits

This article presents a multilayer graphene nanoribbon (MLGNR)‐based single‐tier on‐chip nanoscale via‐interconnect scheme (VIS), which combines the vertical MLGNR via and horizontal MLGNR interconnect, as a prospect for monolithic 3D (M‐3D) integrated circuits (ICs). To go beyond the simplifying assumptions of perfect MLGNR and conventional skin‐effect, this study incorporates the impact of edge‐ and substrate‐induced scatterers in a realistic MLGNR and considers the 1D skin depth formula for MLGNR‐based on‐chip interconnect and via. A combined equivalent circuit model is developed to analyze the challenges induced by scatterers, skin‐effect, and crosstalk effect in perfect MLGNR VIS ( P ‐VIS) and realistic MLGNR VIS ( R ‐VIS). The results show that for width in the range of 5–30 nm, P ‐VIS outperforms R ‐VIS in terms of crosstalk delay. Moreover, at high frequencies ranging from 1 to 10 4 GHz with a width of 16 nm, R ‐VIS demonstrates a performance decline of 243.18% (5.3934 × 10 3 %) for L = 4.8 μm (1 mm), respectively, in comparison with P ‐VIS. Hence, in order to leverage the potential of MLGNR‐based VIS for M‐3D ICs at high frequencies, it is imperative to integrate Li‐intercalation doping and mitigate the impact of edge and substrate scatterers in MLGNR.