Compact XOR/XNOR-Based Adders and BNNs Utilizing Drain-Erase Scheme in Ferroelectric FETs

ABSTRACT Compact and energy-efficient computing avenues such as in-memory computing and processing-in-memory (PIM) are being actively explored to address the limitations of the sparse vonNeumann computing systems. The recent advancements in the field of emerging non-volatile memories (e-NVMs), such as FeFETs, RRAMs, MRAMs, etc., have propelled the development of the PIM technique where the logic operations are performed in situ (where the operands are stored) to reduce the energy draining data movement. Considering the promising potential of the doped-hafnium oxide (HfO2) based FeFETs, such as CMOS compatibility, high scalability, high integration density, and fielddriven programming capability, in this work, for the first time, we propose a novel input-to-voltage mapping scheme and exploit drain-erase phenomenon to realize compact and energy-efficient majority logic gate using a single Fe-FDSOI FET, XOR and XNOR logic gates using two Fe-FDSOI FETs. Furthermore, utilizing the proposed FeFET-based XOR and XNOR logic design, we demonstrate a compact implementation of a half adder (using 3 FeFETs) and full adder (utilizing only 9 FETs) which outperforms the CMOS and prior eNVM-based implementations in terms of area and energy. Moreover, we also propose a modified XNOR-cell design utilizing 4 FeFETs for performing bitwise count operations in binary neural networks.