Single-Chip 30 GHz SiGe Sub-Sampling PLL with 28.3 fs Jitter

We demonstrate a phase locked loop (PLL) in a 45 nm PDSOI process with SiGe heterojunction bipolar devices (HBTs). The PLL has an output frequency centered around 30 GHz and exhibits low jitter and in-band phase noise. Measurements demonstrate -100.9 / -116.6 / -126.9 dBc/Hz phase noise at 1 kHz / 1 MHz / 10 MHz offsets, with integrated jitter of 28.3 fs (rms). It combines the far-out low phase noise performance of a SiGe HBT LC-VCO with a sub-sampling loop that significantly reduces the in-band noise contribution from loop filter components. The 45 nm PDSOI FETs enable sub-sampling bandwidth over 30 GHz. The loop filter features a wide degree of tunability, enabling optimization of in-band and far-out phase noise.