A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB

This paper presents a $34-35 \mathrm{GHz}$ integer-N sub-sampling phase-locked loop (PLL) in a 45nm PDSOI BiCMOS ($0.1 \mu \mathrm{~m}$ SiGe HBT integrated with 45 nm PDSOI) technology. This monolithic integration takes full advantage of SiGe HBT’s low noise and PDSOI’s low power consumption characteristics. The designed and implemented PLL is tested with a low phase noise of $-123.69 \mathrm{dBc} / \mathrm{Hz}$ at 1 MHz offset and an integrated RMS jitter of 37fs. While dissipating 63mW, it realizes a jitter FoM of -250.7dB (FLL on) and -252.2dB (FLL off).