Efficient Approximate Adders for Image Processing Applications

This effort sacrificed accuracy in order to design fast, energy-efficient adders. In order to minimize propagation delay and reduce power consumption, the proposed design truncates half of the adder area. Additionally, internal stage input-output pipelining to the parallel prefix adder can further optimize propagation delay to half of its original value. By significantly raising the approximation adder error, the MSP minimizes the parameters while utilizing the exact calculation and LUTs as resources. In comparison to the current LEADx and APEx, our proposed adder is now efficient in terms of parameters. Xilinx Vivado is used to synthesize the design, simulation, and efficacy of the suggested method. As a case study, the suggested approximation adders are applied in a video encoding application. For video encoding applications, LEADx provided superior quality when compared to other types of approximation adders. Thus, our suggested approximate adders can be useful in efficient FPGA designs of error-tolerant applications.