On the Prevention of Coherence-Induced Static Noise Margin Degradation of SRAM Cells

This paper proposes an enhanced cache organization to mitigate the coherence-induced static noise margin degradation of cache memory cells. The enhancement is conducted based on the outcomes of an analysis intended to investigate the causes of static noise margin degradation in the SRAM cells. The empirical study demonstrates that the unbalanced distribution of data blocks associated with different coherency states over lines of a cache set can also be interpreted as a cause of the static noise margin degradation. Based on the findings, an aging-aware cache replacement policy is presented to balance the distribution of dirty/clean data blocks over the cache lines. To this intent, the decision tree of the Pseudo-LRU is revisited concerning the coherency state of cache lines and the type of address conflict miss. Using the enhanced cache, the hold and read static noise margin degradation are improved by about 9.9% and 11.5%, with less than 1.0% reduction in the cache hit ratio and negligible area and energy overheads.