Combinational Standard Cells Adjacency Effect Analysis on Soft Error Occurrence Using Device-Level Simulations

In this paper, the vulnerability of combinational standard cells to single/multiple event transients is investigated. To this end, extensive 3D-TCAD simulations are conducted for standard cells by considering different cell adjacencies, and the electrical responses are analyzed. In this regard, first, the effect of various particle linear energy transfers and angles is investigated at different parts of standard cells. Then, the effect of particle strike has been evaluated on adjacent identical and non-identical standard cells. Eventually, the probability of failure of the cells by considering their adjacent cells is calculated. The obtained collected charges from device-level simulations reveal that the NAND is the most vulnerable standard cell among the other investigated cells against particle strike. Also, the composition of NOR-INV and NAND-INV cells are the least and the most vulnerable adjacent cells among other investigated compositions, respectively.

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Published
2024-10-16
DOI
https://doi.org/10.1109/cpsat64082.2024.10745376
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
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article
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article

Combinational Standard Cells Adjacency Effect Analysis on Soft Error Occurrence Using Device-Level Simulations

Hamid R. Zarandi, Amir M. Hajisadeghi, Ali Asghar Zarei
Integrated Circuits and Semiconductor Failure Analysis
article

Combinational Standard Cells Adjacency Effect Analysis on Soft Error Occurrence Using Device-Level Simulations

Hamid R. Zarandi, Amir M. Hajisadeghi, Ali Asghar Zarei
article en

Abstract

In this paper, the vulnerability of combinational standard cells to single/multiple event transients is investigated. To this end, extensive 3D-TCAD simulations are conducted for standard cells by considering different cell adjacencies, and the electrical responses are analyzed. In this regard, first, the effect of various particle linear energy transfers and angles is investigated at different parts of standard cells. Then, the effect of particle strike has been evaluated on adjacent identical and non-identical standard cells. Eventually, the probability of failure of the cells by considering their adjacent cells is calculated. The obtained collected charges from device-level simulations reveal that the NAND is the most vulnerable standard cell among the other investigated cells against particle strike. Also, the composition of NOR-INV and NAND-INV cells are the least and the most vulnerable adjacent cells among other investigated compositions, respectively.

Amirkabir University of Technology (IR)
Openalex Percentile: Top 82%
Integrated Circuits and Semiconductor Failure Analysis
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