XOR-Free Approach for Implementation of Polar Encoder

This letter presents a new algorithmic approach to construct an XOR-Free architecture for a nonsystematic polar encoder (NSPE). Optimization of XOR units is the main concern while implementing NSPE, which consumes a significant amount of dynamic power. To generate polar sequences of code length N, the approach uses <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(N/2)-1$ </tex-math></inline-formula> binary patterns extracted from the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(N/2)^{\mathrm { th}}$ </tex-math></inline-formula> order generator matrix <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{N/2}$ </tex-math></inline-formula> instead of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{N}$ </tex-math></inline-formula>. The algorithm reduces the logical operations by virtue of the recursive patterns, thereby improving hardware (HW) cost. The pattern logics are inferred with 2:1 multiplexers and inverters, making the implementation XOR-Free. An auto HDL code generation script is written targeting variable code lengths (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{^{{3}}} \leq {N} \leq 2{^{{10}}}$ </tex-math></inline-formula>) for direct comparison with similar approaches, viz. stage folded and punctured NSPE design. The results show that the proposed architecture improves area by 31%–83% and power consumption by 15%–57% for various N and code rates (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R{=}1$ </tex-math></inline-formula>, 1/2) on Virtex-6 FPGA devices.