DESIGN OF A 24.5 GHZ CMOS LOW NOISE AMPLIFIER USING 0.13-µM TECHNOLOGY FOR 6G WIRELESS APPLICATIONS

The need for high-performance circuit designs is growing as wireless communication technologies continue to advance and support newer generations of wireless applications. Much emphasis has been focused on the possibility of the 24 GHz frequency band in next-generation wireless networks, including 5G and beyond. Designing a low noise amplifier (LNA) operating at 24 GHz presents several challenges. The primary concerns include achieving high gain, low power consumption, low noise figure, and while maintaining good linearity and stability. This paper presents the design, simulation, and layout of a CMOS LNA optimized for operation at 24.5 GHz frequency, targeting 6G and beyond wireless communication applications. The proposed LNA employs three stages with a cascode topology at the first stage and follow by a common source stage at second and third stage. The three stages help to achieve high gain, and the source degeneration inductor at the first stage helps to improve linearity. Extensive simulations were conducted using a 0.13-µm CMOS technology, demonstrating a peak gain of 21 dB and a noise figure of 5.6 dB at 24.5 GHz. The LNA also exhibits good linearity and stability over a wide bandwidth. The performance metrics were validated through simulation and comparison, showcasing the feasibility of the designed LNA for 6G applications. This work contributes to the advancement of CMOS-based radio frequency (RF) front-end designs for next-generation wireless communication systems.