Maximum Output Power Design on an 85 kHz Class-D Half-Bridge ZVS Inverter with Power-MOSFETs

This paper analyzed and verified the condition for obtaining the maximum output power with an 85 kHz class-D half-bridge zero-voltage-switching (ZVS) inverter. The shunt capacitance in the class-D half-bridge ZVS inverter is formed by nonlinear parasitic capacitance and linear external capacitors. The design equation of the shunt capacitance is derived. For verification, two class-D half-bridge inverters are designed with Si-MOSFETs and SiC-MOSFETs in four specifications. The simulated and experimental waveform verified the validity of the design procedure for achieving the ZVS operation, and the measured result verified the analysis of output power characteristics with good consistency. Furthermore, the relationship between the maximum output power and parasitic capacitance is analyzed. It is clarified that the power MOSFET with smaller parasitic capacitance can obtain higher maximum output power. By comparing the maximum output power between the Si-MOSFET and SiC-MOSFET, it is indicated that the SiC-MOSFET with smaller parasitic capacitance can obtain higher maximum output power than Si-MOSFET, verifying the condition for obtaining the maximum output power.