Fault-tolerant and Area-efficient EXOR Circuit Design using QCA Nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology offers efficient design of digital circuits.High-speed, low-energy consumption, low-area requirement are the significant features of QCA nanotechnology.An exclusive-OR (EXOR) gate has been applied to design various digital applications.Hence, an efficient EXOR gate design needs to be implemented.This research work proposes a translation-based three input EXOR gate in QCA nanotechnology.The proposed EXOR gate is extensively explored for fault analysis.The power dissipation analysis is also given for the proposed EXOR gate.The proposed EXOR gate has only 10 cells and two clock latencies.For the performance evaluation of the proposed EXOR gate, a comparative analysis is provided for different parameters.The proposed EXOR gate outperforms in comparison to the existing EXOR gates in QCA nanotechnology.It improves the cell area by 25% and the layout cost by 23.08% in comparison with the best-reported three input EXOR gate in the literature.The efficacy of the proposed three input EXOR gate for the digital circuit implementation is noted by designing a 1-bit full subtractor, a 4-bit parity checker, and a 4-bit binary to gray (B2G) code converter.