Millimeter-Wave CMOS Devices Design With Mobility Enhancement and Parasitic <i>RC</i> Suppression for Super-350 GHz f_T and f_MAX in Multiring nMOSFETs

Multifinger (MF) and multiring (MR) nMOSFETs were designed and fabricated in 40-nm CMOS technology to explore the layout-dependent effects (LDEs) in terms of uniaxial stress, effective mobility (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {eff}}$ </tex-math></inline-formula>), as well as parasitic resistances and capacitances (RC) responsible for the high-frequency performance like unit current gain cut-off frequency, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and maximum oscillation frequency, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula>. The experimental results prove the advantages of MR nMOSFETs, such as the higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {eff}}$ </tex-math></inline-formula> and transconductance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{\text {m}}$ </tex-math></inline-formula>), as well as the smaller parasitic source resistance and gate resistance, which can yield record high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> in 40 nm CMOS technology, up to 360- and 402-GHz, that is 60 and 115-GHz higher than that of MF nMOSFET with the same finger number and width. This superior <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> keep even better than 22 and 14 nm FinFETs. Besides, new methods have been developed to realize accurate extraction of the parasitic RC and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {eff}}$ </tex-math></inline-formula> in sub-40 nm nMOSFETs with various layouts. The precise parameters extraction and modeling of the LDE can facilitate nanoscale device layout optimization, aimed at super-350 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> for mm-wave CMOS circuit design.