The Josephson Balanced Comparator as a Sensor to Monitor Clock Sources for RSFQ/ERSFQ Circuits

The Josephson balanced comparator (BC) is a key component for all RSFQ/ERSFQ logic cells. Its frequency-dependent properties (gray zone and threshold current value) define the maximum clock frequency and bit error rate (BER) of RSFQ/ERSFQ circuits. The balanced comparator can also be used for various monitoring purposes. In this paper, we focus on clock sources and analyze several of them by means of BCs. We show experimentally how local overheating, associated with sub-optimally designed analog clock sources, can compromise the HF performance of a balanced comparator as well as an RFSQ/ERSFQ circuit on the same chip. We also investigate a clock source based on an external HF generator followed by an on-chip DC/SFQ converter and a frequency doubler. We use the balanced comparator's performance to optimize the on-chip part of the clock source at HF. In addition, we verify the advantage of overshunting the comparator driver to achieve higher clock frequency and lower BER. All test circuits were designed for the SFQ5ee fabrication node at MIT-LL, but conclusions can be applied to other fabrication processes.