Technical challenges designing a prototype common readout board for LHCb future upgrades

Abstract The LHCb Upgrade I data acquisition system is designed to operate at a bunch crossing of up to 40 MHz with a mean of six proton-proton interactions per bunch crossing, the detector produces an input bandwidth to the data acquisition system of 5 TB/s. For LHCb Upgrade II, the mean number of proton-proton interactions per bunch crossing will increase to up to 40 while the input bandwidth of the data acquisition system can reach 25 TB/s or more. The data acquisition system is a single stage readout followed by event-building on a local area network and by a two-stage filtering using heterogeneous compute elements. Discussed here is the design process of the custom FPGA board, called PCIe400, for the readout of LHCb Upgrade II. The PCIe400 intends to increase output bandwidth by four and processing capabilities by twelve compared to the readout board of LHCb Upgrade I. Its design is a challenge as it embeds over 100 Gbit/s serial links and Altera's flagship FPGA, Agilex 7 M-series FPGA. Extensive simulations were conducted to address key design considerations including thermal dissipation, power distribution, and signal integrity.