Modeling and Designing a Combination Lock State Machine by Using VHDL

Abstract: Recently, the electronic devices enter our daily life in many places, to make it more convenient. However, the aim of this paper, it will be illustrated how to model and design a digital machine by means of VHDL (Very High Speed Integrated Circuit) Hardware Description Language very high modleng. However, the machine that intended to be designed is a Combination Lock State Machine, one of which its output is activated after a certain binary sequence is received while the other output is dependent on both current and past history of the inputs (Mealy Machine). The design will be carried out via Altera Max+plus II framework or program; in addition to that, the design will be inspected and verified by a simulation waveform to make sure that all the required specification is achieved.