Gate-All-Around Silicon Nanowire Field Effect Transistor Behavior at High Gate Voltages

This paper presents an observance of a novel phenomenon in gate-all-around field effect transistor (GAAFET) structures with a 1D active semiconducting channel. In this work, a small-diameter silicon nanowire is modeled, and its behavior is studied. The GAAFET device is modeled using an ensemble Monte Carlo (EMC) simulator in which the electrostatic potential landscape in the nanowire is solved self-consistently using the Gauss Law in integral form. The model captures an unexpected operation region. It is observed that after certain voltage values of gate-to-source voltage, $\mathbf{V}_{\mathrm{gs}}$, the device shows a negative differential resistance (NDR), with the current I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> decreasing while increasing V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</inf>.