Design of the <i>E</i> -Band Power Amplifier With Cascode Gain- and Power-Boosting and Shunt Capacitance Matching Improvement

This letter presents an E-band power amplifier (PA) fabricated in 65-nm CMOS technology. This PA adopts a three-stage design approach and a cascode structure to extend the supply voltage for higher gain and output power. The two-way power-combining technique is exploited to further improve the power delivered. By introducing an additional shunt capacitance, the insertion loss is reduced in the interstage matching before the power stage. This PA exploits the transformer coupling technique for interstage connection and compact layout techniques to make the PA suitable for millimeter-wave (mmW) applications. The PA provides 21.2 dBm of saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula>), 24.6 dB of transducer gain, and 20.6% of power-added efficiency (PAE) under a multiple supply voltage of 1.2 and 2.4 V and current consumption of 150 and 220 mA at 80 GHz, respectively. The PA occupies a core die size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$800\times 360~\mu $ </tex-math></inline-formula>m. To the author’s knowledge, it is the first publication to improve the performance using shunt capacitance to improve the performance under cascode configuration.