Realization of CMOS operation in 3-dimensional stacked FET with self-aligned direct backside contact
Abstract Beyond MBCFET TM technology, the 3-dimensional stacked FET (3DSFET) emerges as a promising contender, featuring a structure that stacks NMOS and PMOS vertically to continue area scaling and improving the energy efficiency of logic technology. In this study, we report successful CMOS operations of 3DSFET by implementing vertical integration of a Source/Drain (SD), metal gate, and contacts including Self-Aligned Direct Backside Contact (SA-DBC) in an industry-compatible Contacted Poly Pitch (CPP) of 48 nm.
Authors
- Daihong Huh
- Daewon Ha (ORCID: https://orcid.org/0000-0002-9061-8626)
- Juhun Park (ORCID: https://orcid.org/0009-0001-7553-3069)
- Jaihyuk Song
- T.I. Kim
- Sunjung Lee (ORCID: https://orcid.org/0000-0002-5177-0916)
- Deukho Yeon
- Jinwook Yang
- Sung-Il Park (ORCID: https://orcid.org/0000-0001-9474-4876)
- Jejune Park
- Sanghyeon Kim (ORCID: https://orcid.org/0000-0002-2517-4408)
- Jinho Bae (ORCID: https://orcid.org/0000-0002-5298-0122)
- Seungjun Lee (ORCID: https://orcid.org/0009-0001-4314-0260)
- Jaehyun Park (ORCID: https://orcid.org/0000-0002-5264-6941)
- Jae Won Jeong (ORCID: https://orcid.org/0000-0003-3879-3918)
- Dahye Kim
- Jung-Han Lee (ORCID: https://orcid.org/0000-0002-1974-8807)
- Soomin Son
- Su Jin Ahn
- Sangjin Hyun
- Kyuman Hwang
- Seungeun Baek
- S.W. Park
- Jinchan Yun
- Chuljin Yun
- Bong Jin Kuh
Institutions
- Samsung (South Korea) (KR)
Publication Details
- Journal
- Japanese Journal of Applied Physics
- Published
- 2024-11-07
- DOI
- https://doi.org/10.35848/1347-4065/ad8fb5
- Citations
- 2
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.42