Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors

The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation attempts. In this paper, one limitative factor is identified that must be addressed to finally push automation tools into the analog integrated circuit design flow: accurate assessment of post-layout performance degradation. For this purpose, a performance-driven placement generator highly integrated with off-the-shelf tools already adopted by circuit/layout designers, i.e., circuit simulator, verification tools (layout-versus-schematic) and layout extractor, is proposed. Toward maximum post-layout accuracy, this generator promotes an exhaustive simulation-based synthesis, extracting, simulating and verifying the post-layout functional behavior of every candidate floorplan. Additionally, to bypass the time-consuming extractions/simulations and accelerate synthesis, novel post-layout performance regressors based on different highly accurate machine learning techniques are also being developed. The data used to train them can be directly and conveniently acquired from previous precise post-placement simulations. Experimental results over two analog circuit structures show that a set of performance regressors based on tree-based models, while operating on compressed design spaces, allow for the speeding up of synthesis by more than 20×, which represents a step toward an efficient fully automatic performance-driven analog integrated circuit design flow.