Parallel Per-tile Activation with Linear Superposition of Thermal Response for Solving Arbitrary Power Pattern in 3DIC Thermal Simulation

A large on-chip peak temperature and thermal gradient, caused by localized hotspots and cross-die thermal coupling, can severely impact transistor performance, stress, aging, electromigration (EM), voltage drops, and timing. Generating static and transient chip thermal profiles with traditional FEM/CFD methods have prohibitively expensive computational requirements, especially for three-dimensional integrated circuits (3DIC). Even though data driven based deep learning approaches can significantly improve the efficiency of obtaining accurate thermal profiles, large amounts of high-quality and diverse training data are required. Therefore, there is an urgent need for improving the data/training efficiency and generalizability of deep learning-based models for thermal applications. This investigation leverages the “linear superposition principle” for linear systems and divides a complex power pattern into “per-tile activation” scenarios. The predictions from machine learning (ML) model trained on per-tile activation data, which consists of power and thermal response pairs, are then linearly combined to generate the total thermal response for a given arbitrary power pattern. This novel approach can substantially reduce the infinite design space of the power patterns to a small finite design space, and it has been validated that it can significantly improve the generalizability and training efficiency of deep learning models. The proposed approach can be applied to static and transient chip thermal simulation for 3DIC.CCS CONCEPTS• Computing methodologies • Applied computing • Mathematics of computing