Enabling Risk Management of Machine Learning Predictions for FPGA Routability

Machine Learning (ML) models sometimes make inaccurate predictions for the routability of field-programmable gate array (FPGA) circuit designs. This risks time wasted attempting to route an unroutable design or the premature termination of a routable design’s compilation. While improving model accuracy is beneficial, we explore a complementary approach to mitigate the risk of inaccurate predictions by assessing the confidence of ML models. This approach could allow individuals to customize their own trade-off for the competing risks of wasted time and premature compilation termination. In this paper, we introduce a novel mixture of experts ML system for FPGA routability prediction and further quantify the confidence calibration of this system to determine its suitability as a risk management tool. We evaluate our prediction system for the purpose of enabling user risk management in FPGA routability prediction, comparing against a baseline inspired by prior work. Our evaluation finds our approach to achieve almost $2 \times$ the precision in risk trade-off between time wasted on unroutable designs and premature termination of routable designs. CCS Concepts • Hardware $\rightarrow$ Reconfigurable logic and FPGAs; Physical design (EDA); • Computing methodologies $\rightarrow$ Machine learning