Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization

Flip-flops are simultaneously endpoints of combinational logic timing paths and leaf nodes of clock networks. Hence, flip-flop placement significantly affects both circuit timing and clock network power. Previous works on flip-flop clustering/placement are mostly based on geometric models, which have limited accuracy for timing and power estimation. Moreover, these methods cannot account for the impact of clock tree synthesis parameters. In order to overcome this drawback, we develop CNN-based circuit timing and clock network power models. The CNN models are further applied to guide flip-flop centric incremental placement for simultaneous timing and clock network power optimization. Experimental results on benchmark circuits show that our method outperforms state-of-the-art previous works on timing, power, and computation runtime. CCS Concepts • Hardware → Electronic design automation.