Current Consumption Modeling of Logic Cells Based on Measurements for Side-channel Attack Simulation

Side-channel attacks, which estimate the internal secret key by analyzing the radiated electromagnetic waves generated by the current consumption of the encryption circuit, represent a realistic threat. To achieve resistance against side-channel attacks, the current consumption of the encryption circuit must be independent of the secret key. In circuit design, side-channel resistance should be evaluated by simulation to reduce rework costs. For this purpose, a highly accurate power model for logic cells is needed to represent the minute differences in power consumption that vary with input during the encryption process. However, in ASIC design and FPGAs, models are provided only to estimate overall power consumption. In this paper, we propose a method to extract the power consumption of a single logic cell with high accuracy from power consumption measurements of multiple same logic cells to avoid background noise, and show that the increase in peak power consumption with the number of elements when NAND logic is implemented is captured linearly. This measurement method archives express the difference in power consumption caused by the different directions of logic transitions.