Automated Method to Synthesize RLCK-Circuits from S-Parameters

To understand and control parasitic elements on the PCB-, package- and chip-level, designers require compact yet precise circuit models. The PEEC methods and "classical" parasitic extraction exhibit distinct disadvantages when applied to systems comprising layered planar conductors: Due to their reliance on partial inductances, the resulting models are not very intelligible and comparably complex. In contrast, our approach synthesizes highly compact and interpretable circuits based on loop inductances. Our novel method is more general than the algorithm by YOUNG. At the core of our technique is an exact equivalent circuit of multi-port S-parameters, applicable also to electrically large systems and radiation coupling.