ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging Effects

Integrated circuits at advanced technology nodes are prone to process variations and early life failures due to aging. Variations in transistor parameters lead to a degraded on-current which, in turn, results in increasing gate-level propagation delay. Similarly, threshold voltage shifts due to aging effects result in increased path delays and erstwhile latent defects manifesting as early life failures (ELFs). We propose ML-TIME, a novel machine learning-based framework to simulate path delays in an integrated circuit in the presence of process variations and aging effects. While conventional static timing analysis (STA) tools can only compute path delays at well-defined process-voltage-temperature corners, ML-TIME can be used to obtain a statistical distribution of the path delays under user-defined process variations and aging specifications. Such distributions can be used to identify paths that are susceptible to either process variations or aging effects or both and can enable designers to make remedial changes. Simulation results across multiple benchmarks and standard cell libraries demonstrate that the MLTIME can accurately predict critical path delays under variations and aging, with an error margin of less than 1.7%, all without the need for computationally expensive circuit simulations.