TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path

In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D Integrated Circuits (ICs). Recent advancements in 3D vertical interconnection technology have enabled 3D interconnections with reduced area overhead, potentially enhancing 3D IC performance in terms of timing, power, yield, and cost. However, despite the increased inter-die connection capacity enabled by fine-pitch 3D vias, research on 3D IC partitioning methods for timing improvement remains insufficient. This paper proposes a partitioning and placement method that optimizes the timing of 3D ICs by leveraging the increased inter-die connection capacity provided by fine pitch 3D vias. By using the Leiden algorithm and unsupervised GNN, we achieve optimal partitioning without relying on the results of 2D placement or additional training data. Our method employs balanced COP-KMeans to incorporate critical path optimization into partitioning, while ensuring balanced cell allocation across dies, thereby maximizing the area benefits of 3D ICs. Additionally, we optimize the timing of 3D ICs through 3D cell placement with critical net weight adjustments and a novel 3D via placement approach that differs from traditional 3D Half-Perimeter Wire Length (HPWL) optimization perspectives.