DEFending Integrated Circuit Layouts

Modern integrated circuits (ICs) require a complex, outsourced supply-chain, involving computer-aided design (CAD) tools, expert knowledge, and advanced foundries. This complexity has led to various security threats, such as Trojans inserted by adversaries during outsourcing, but also run-time threats like physical probing. Our proposed design-time solution, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DEFense</i>, is an extensible CAD framework for holistic assessment and proactive mitigation of multiple prominent threats. The goal is to prioritize security concerns during the physical design of ICs, alongside traditional power, performance, and area (PPA) objectives. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DEFense</i> utilizes an iterative and modular approach to assess and mitigate various known vulnerabilities in the IC layout, which are targeting on sensitive active devices and wires. It is a flexible and extensible scripting framework without the need for modifications to commercial CAD flows, yet with the same high level of design quality. We have conducted extensive case studies on representative modern IC designs to “DEFend” layouts against Trojan insertion, probing, and crosstalk attacks. We are providing the framework to the community.