SPICE based SI-PI co-simulation Framework to optimize Die-Package-PCB to meet LPDDR5(x) Performance in Automotive and Edge MPU-MCU

This paper represents SPICE based Signal Integrity (SI) and Power Integrity (PI) co-simulation framework, which would help in accurate modeling as well as optimizing the system-level components including Die, Package and printed circuit board (PCB) to meet the LPDDR5(x) performance. The proposed framework has integrated all the system level components starting from 32-bit (LP)DDR SPICE IO bank, Die redistribution layer (RDL) SPEF (standard parasitic extraction format) for signals & power as a Die component, interconnects modelled as S-parameters, and the DRAM model which has package, RDL interconnect model & IBIS from DRAM vendor. The DDR protocol operates at burst which may also align with the system resonance frequency resulting into significant on-die power ripple, and due to that timing would be impacted. The SoC Power RDL SPEF is required to accurately model die-capacitance (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DIE</inf>) & die-resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DIE</inf>) so that power distribution network (PDN) resonance peak amplitude & frequency can be tuned to get the on-die ripple & timing within specifications. This paper would also cover the data pattern recommendation in order to capture the impact of power supply induced jitter (PSIJ) and inter-symbol interference (ISI) & crosstalk due to interconnects on timing.