Design Decoupling of Inner- and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling

Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner - and outer-gates in gate-all-around nanosheet FETs. Trade-off between short-channel effects (SSAT), external resistance (REXT), effective capacitance (CEFF including parasitic capacitance CPARA) favors for a more aggressive outer-LG scaling (reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm { C}}_{\mathrm { PARA}}$ </tex-math></inline-formula> and/or relaxes contact length, LCNT) keeping inner-LG relaxed (controls REFF, SSAT). Up to 10% speed-at-iso-leakage and speed-at-iso-power, and 15% power-at-iso-speed gains are possible with this unique design available in GAA-NS based devices, allowing for multi-node GAA extension without scaling more fundamental geometry parameters like thickness of NS.