Three-Dimensional Electro-Thermal Coupling Temperature Evaluation Modeling of Wire-Bonded Power Chips Under Surge Conditions

The relationship between the failure of power semiconductor chips under surge conditions and the resultant high temperatures due to self-heating underscores the importance of acquiring the chip's temperature during surge conditions for reliability assessment. However, the current experimental approach for directly obtaining the chip's transient junction temperature is not readily applicable in practical engineering under surge conditions. Hence, there is a critical need for accurate modeling to calculate the chip's transient temperature rise. This article presents a pioneering fully-coupled electro-thermal model that integrates chip physical properties with three-dimensional (3-D) packaging structures. It facilitates the computation of the chip's 3-D temperature distribution under surge conditions without resorting to destructive surge experiments. The article elucidates the modeling principles and process, demonstrating that the surge I-V trajectory and temperature distribution derived from the model closely match experimental measurements.