Model-Order Reduction of Multistage Cascaded Models for Digital Predistortion

This paper explores the benefits of utilizing multistage cascaded (CC) behavioral models for digital predistortion (DPD) linearization of wideband high-efficiency power amplifiers (PAs). To reduce the computational complexity of these multistage CC behavioral models, a model-order reduction technique based on a greedy algorithm is proposed. The advantages of employing CC DPD models with gradient descent parameter identification, as opposed to single-stage DPD models with least squares parameter identification, are extensively demonstrated and analyzed. The trade-off among linearity, power efficiency and computational complexity is evaluated considering the linearization of a high-efficiency pseudo-Doherty load-modulated balanced amplifier (PD-LMBA). Using the proposed pruning strategy for CC DPD models, we demonstrate a significant reduction in the number of parameters needed to linearize the PD-LMBA. The PA operates at an RF frequency of 2 GHz and delivers a mean output power of 40 dBm with an approximately 50% power efficiency when driven by 5G new radio signals with up to 200 MHz bandwidth and an 8 dB peak-to-average power ratio.

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Publication Details

Journal
IEEE Journal of Microwaves
Published
2024-11-06
DOI
https://doi.org/10.1109/jmw.2024.3483458
Citations
6
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
1.11

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article

Model-Order Reduction of Multistage Cascaded Models for Digital Predistortion

Gabriel Montoro, Raúl Criado, Pere L. Gilabert, Kevin Chuang et al.
6 citations
IEEE Journal of Microwaves
Analog and Mixed-Signal Circuit Design
1.11
article

Model-Order Reduction of Multistage Cascaded Models for Digital Predistortion

Gabriel Montoro, Raúl Criado, Pere L. Gilabert, Kevin Chuang, Wantao Li, William Hedley Thompson
article en
6 citations

Abstract

This paper explores the benefits of utilizing multistage cascaded (CC) behavioral models for digital predistortion (DPD) linearization of wideband high-efficiency power amplifiers (PAs). To reduce the computational complexity of these multistage CC behavioral models, a model-order reduction technique based on a greedy algorithm is proposed. The advantages of employing CC DPD models with gradient descent parameter identification, as opposed to single-stage DPD models with least squares parameter identification, are extensively demonstrated and analyzed. The trade-off among linearity, power efficiency and computational complexity is evaluated considering the linearization of a high-efficiency pseudo-Doherty load-modulated balanced amplifier (PD-LMBA). Using the proposed pruning strategy for CC DPD models, we demonstrate a significant reduction in the number of parameters needed to linearize the PD-LMBA. The PA operates at an RF frequency of 2 GHz and delivers a mean output power of 40 dBm with an approximately 50% power efficiency when driven by 5G new radio signals with up to 200 MHz bandwidth and an 8 dB peak-to-average power ratio.

IEEE Journal of MicrowavesVol. 5(1)
Analog Devices (United States) (US), Universitat Politècnica de Catalunya (ES)
Generalitat de Catalunya, Ministerio de Ciencia e Innovación, Agencia Estatal de Investigación
Affordable and clean energy
Openalex Percentile: Top 24%
Analog and Mixed-Signal Circuit Design
1.11
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