Co-Designed Silicon Photonics Chip I/O for Energy-Efficient Petascale Connectivity

Data volume in hyperscale computing systems has surged exponentially over the past decade, notably driven by artificial intelligence (AI)/machine learning (ML) applications and the emergence of large-scale generative AI models. An urgent need arises for ultrahigh-bandwidth and energyefficient communications among compute clusters to support the application demands. Embedded silicon photonics (SiPh) promises to enable petascale system-wide connectivity by integrating optical input/output (I/O) directly into the compute socket. SiPh microresonator-based modulators and filters, known for their excellent wavelength selectivity and compact footprints, offer an elegant solution for realizing dense wavelength-division multiplexing (DWDM) links with ultrahigh bandwidth density, leveraging the latest advances in optical frequency comb (OFC) sources and 3-D integration with electronics. In this work, we present our scalable DWDM link architecture, designed with co-packaging in mind. We report device-level measurements of key components and validate comb-driven end-to-end data transmission. These results demonstrate promise in realizing co-packaged optical I/Os with shoreline and aerial bandwidth densities beyond 4 Tbps/mm and 17 Tbps/mm2 while consuming sub-pJ/b energy, paving the way for petascale photonic connectivity for energy-efficient computing.