Rate Matching and Interleaving Hardware Sharing Design for Wireless Terminal in Internet of Vehicles

Reducing the power consumption of baseband chips in wireless terminals of the Internet of Vehicles (IoV) is a great challenge. Among them, the rate matching and interleaving hardware module occupies a significant portion of power consumption in the baseband chip, so it is of great significance to design a low power rate matching and interleaving hardware. The interleavers used in 4G LTE and 5G NR/ 6G have not been merged into a single architecture. It is possible to use the same hardware for different communication standards to reduce hardware resources and power consumption. This paper studies the rate matching and block interleaving of turbo codes, convolutional codes, polar codes, and LDPC codes used in 4G LTE and 5G NR/ 6G communication links. With regard to the different algorithms for these four types of encoding, the sharing design is carried out on the hardware structure. In this experiment, according to the proposed storage and interleaving sharing scheme for hardware design and hardware implementation, the memory area of 0.1 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and power consumption overhead of 4.33 mW are obtained based on the SMIC 28 nm process and the operating frequency of 50 MHZ. This achieves the maximum hardware reuse of four encoding schemes in the downlink communication link of 4G LTE and 5G NR/ 6G, and reduces power consumption.