Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoC

Managing cache coherence is essential for optimizing computing performance and energy efficiency in modern multi-/many-core systems. Enabling cache coherence in scalable agile hardware architectures, particularly within RISC-V-based architectures, demands further optimizations regarding interconnect fabric, memory hierarchy, and core-level modifications. In this work, we present a modular and seamless data cache subsystem extension for RISC-V-based multi-core architectures. The proposed data cache sub-system features a full hardware method for cache coherence based on a snooping coherence scheme. The cache sub-system supports scalable multi-core architectures with different core counts. For evaluation, a coherent multi-core architecture with four RISC-V cores is implemented with the proposed data cache sub-system targeting an AMD/Xilinx Virtex Ultrascale+ FPGA device. Several benchmark kernels are used for performance evaluation in terms of memory access time, achievable execution time, and cache hit rate. The average achievable cache hit rate is greater than 90 % with a small hardware overhead.