Energy-Efficient and Communication-Aware Architectures for Accelerating Deep Learning Workloads

State-of-the-art deep neural networks (DNNs) have grown increasingly complex, featuring diverse structures tailored to meet the demands of various application domains. Consequently, AI accelerator hardware/software codesign has become essential to achieve high performance while maintaining energy efficiency. One notable challenge arises from sparsity within DNNs, especially in neural networks like Graph Convolutional Networks (GCNs), where the data representation exhibits high sparsity. When pruning techniques are employed to optimize DNNs, they can further contribute to sparse implementations, necessitating a codesign approach. Simultaneously, larger architectures are unavoidable due to the escalating complexity of DNNs. However, monolithic architectures encounter issues related to yield and fabrication costs, primarily due to their substantial area overhead. In response, 2.5D chiplet-based architectures have been proposed for large-scale DNN accelerators, employing small chips called chiplets. Therefore, there is a critical need to design optimized chiplet architectures for AI acceleration. This paper discusses these recent research directions for hardware/software codesign of AI accelerators.