Improving Timing Quality Through Net Topology Optimization in Global Routing

Net topology construction is a major task in global routing of physical design since its outcome impacts the overall performance of the chips. The conventional global routers optimize the net topology considering wirelength, congestion, and timing. In this work, we propose a systematic and practical net topology refinement method to reinforce the timing robustness throughout the whole design process. Precisely, we develop a couple of effective techniques of net topology refinement that can be tightly linked to any of existing commercial and academic global routing tools: (1) a fast net topology exploration and (2) a parallel acceleration of net topology tuning. Through experiments, it is shown that our proposed technique is able to considerably enhance the timing metrics with no degradation in power consumption and wirelength.