RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration

In recent years, Deep Neural Networks (DNNs) have become common in the embedded domain for a wide variety of tasks. However, due to strict area and energy requirements, dedicated accelerators for these networks are necessary. Different architectures to fulfill this role are available, but an accelerator targeting the ultra-low area design point is still missing. In this work, we present an architecture focusing on minimizing resource utilization and energy requirements. We propose a small-scale vector processor that can be integrated into a RISC-V core. Unlike traditional, feature-rich vector instruction sets, we instead determine the most crucial instructions for DNN workloads through hardware-software co-design. To evaluate our implementation, we integrate our vector extension into an open-source RISC-V System-on-Chip, the NeoRV32, and measure the hardware overhead and achieved acceleration of operations commonly found in neural networks. Our results show an acceleration of up to 11.9x on convolutional workloads over the baseline architecture, while we demonstrate that our implementation introduces significantly less hardware overhead than previous works. We provide our work open-source to use for further exploration of low area design of VPUs<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>.<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>https://github.com/itiv-kit/rvve