Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design

It has been widely accepted that multi-bit flip-flops (MBFFs) are indispensable cells to implement low-power chips. Generally, because of their large size, the cell heights amount to multiple rows in order to form shapes of balanced aspect ratio. However, the large size cells with multi-row height adversely affect the quality of placement legalization in physical design, which is mainly due to (1) the increase of displacement distance of MBFF cell instances to acquire enough empty space for legalization and (2) the inconvenience in aligning power/ground rails on a die with the top and bottom boundary of MBFF cell instances, thereby increasing wirelength. In this work, we overcome these two limitations, so that the increase of wirelength should be maximally minimized. Precisely, to overcome limitation 1, we propose a new cell placement solution that is suited for multi-row large size cell instances, and to overcome limitation 2, we devise two types of MBFF cell layout of nearly the same PPA (power, performance, area), one with power rail on the cell boundary and the other with ground rail on the boundary. In the meantime, through experiments with benchmark circuits, it is shown that our design flow integrating the two proposed solutions to limitations 1 and 2 is able to reduce the wirelength of the MBFF instances on final chip by $4.98 \%$ on average over that of the conventional design flow, which leads to improve the worst and total timing slacks by $13.76 \%$ and $18.31 \%$, respectively.