EdgeVision SoC: PPA-Impact of RTL-level Modifications

Racyics GmbH is developing the EdgeVision SoC, a platform for embedded machine learning applications. The SoC has various potential design configurations, e.g. regarding IPs, memories, and clocks. Running the full RTL2GDS flow steps to determine the PPA tradeoffs is very costly. In this paper, we show how RTL Architect by Synopsys enables us to quickly assess the PPA-impact of RTL-level changes in our EdgeVision SoC, without running the entire RTL2GDS flow.