Hardware Design Space Exploration in High-Level Synthesis Backend Featuring Online Arithmetic

Online arithmetic represents a paradigm shift, advocating compact and power-aware hardware designs. It amplifies efficiency through seamless streaming computations and massive parallelism, enabling real-time processing with minimal latency. This paper presents a High-Level Synthesis (HLS) backend framework integrating Online arithmetic beside conventional arithmetic as a dimension of hardware design space. The proposed framework navigates the arithmetic dimension to construct and solve diverse Multi-Objective Mixed Integer Linear Programming (MOMILP) models, tackling resource-constrained scheduling and binding for a given Data Flow Graph (DFG). Additionally, this framework consists of an analytical module comprising mathematical and simulation tools to assess the early termination rate within the resulting scheduled DFG. To this end, we explore design space by deriving and solving the MOMILP models for DFGs sourced from Deep Neural Networks (DNNs). The objective function of the models is minimizing the hardware latency. Furthermore, the experiments compared Conventional and Online arithmetic in terms of hardware resource utilization, revealing the advantages of Online arithmetic in achieving more compact and resource-aware hardware designs. Correspondingly, the early-termination rate was evaluated using the Monte Carlo method and Markov chain, considering different statistical distributions of data bits. These experiments provide valuable insights into the performance and efficiency of the proposed framework, highlighting its potential for real-world applications in hardware design.