Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP Cores

The Intellectual Property (IP) cores are vulnerable to adversaries without authentication methodology. State-of-the-art authentication methodologies are based on pre-redistributed keys generated by Random Number Generators (RNGs). RNGs are usually PUF-based architectures susceptible to machine learning attacks, and Chaos Pseudo Random Number Generators(CPRNG) based architectures are vulnerable to input-based attacks. Establishing feedback between CPRNG and PUF modules to overcome both attacks makes a Hybrid PUF structure. This paper proposes a PUF-CPRNG hardware-based authentication methodology to protect the IP Cores in the System. The Multiple PUF-CPRNG-based Authentication Methodology (MPCAS) leverages its unique characteristics to provide a multi-layered authentication process. This paper discusses the design and evaluation of MPCAS by thwarting various attacks such as linear regression(LR) attack, Becker Attack, Fully Connected Neural Network (FCNN), Random Forest Classifier (RFC), Tree-Based Classifier (TBC), and Replay attacks. The prediction accuracy of the key of the RFC attack and TBC attack is less than $35 \%$, the Becker attack is less than $47.1 \%$, and the LR attack and FCNN network attack is less than $51 \%$. Comparatively, prediction accuracy is improved on an average of $0.8 \%$ to $8 \%$ with other PUF Structures and passes the randomness test by NIST 800-22 Test Suite, Correlation analysis, and ENT Analysis. The proposed Multiple PUF-CPRNG Authentication methodology presents a novel approach to authentication that integrates with 8-bit ALU, C7552 ISCAS’ 85 benchmark circuit, RISC-V processor Core, and Deep Neural Network(DNN). The same has been tested on various hardware platforms, viz. Xilinx Zynq Ultrascale ZCU102 and ZCU104 Silicon on Chip(SOC) FPGA Boards.

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Published
2024-09-16
DOI
https://doi.org/10.1109/socc62300.2024.10737787
Citations
1
Primary Topic
Physical Unclonable Functions (PUFs) and Hardware Security
Type
article
Field-Weighted Citation Impact
0.49
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Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP Cores

Agshare Dheeraj, Amit Acharyya, Pabitra Das, Yv Sai Dinesh et al.
1 citations
Physical Unclonable Functions (PUFs) and Hardware Security
0.49
article

Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP Cores

Agshare Dheeraj, Amit Acharyya, Pabitra Das, Yv Sai Dinesh, Anagha Nimbedkar
article en
1 citations

Abstract

The Intellectual Property (IP) cores are vulnerable to adversaries without authentication methodology. State-of-the-art authentication methodologies are based on pre-redistributed keys generated by Random Number Generators (RNGs). RNGs are usually PUF-based architectures susceptible to machine learning attacks, and Chaos Pseudo Random Number Generators(CPRNG) based architectures are vulnerable to input-based attacks. Establishing feedback between CPRNG and PUF modules to overcome both attacks makes a Hybrid PUF structure. This paper proposes a PUF-CPRNG hardware-based authentication methodology to protect the IP Cores in the System. The Multiple PUF-CPRNG-based Authentication Methodology (MPCAS) leverages its unique characteristics to provide a multi-layered authentication process. This paper discusses the design and evaluation of MPCAS by thwarting various attacks such as linear regression(LR) attack, Becker Attack, Fully Connected Neural Network (FCNN), Random Forest Classifier (RFC), Tree-Based Classifier (TBC), and Replay attacks. The prediction accuracy of the key of the RFC attack and TBC attack is less than $35 \%$, the Becker attack is less than $47.1 \%$, and the LR attack and FCNN network attack is less than $51 \%$. Comparatively, prediction accuracy is improved on an average of $0.8 \%$ to $8 \%$ with other PUF Structures and passes the randomness test by NIST 800-22 Test Suite, Correlation analysis, and ENT Analysis. The proposed Multiple PUF-CPRNG Authentication methodology presents a novel approach to authentication that integrates with 8-bit ALU, C7552 ISCAS’ 85 benchmark circuit, RISC-V processor Core, and Deep Neural Network(DNN). The same has been tested on various hardware platforms, viz. Xilinx Zynq Ultrascale ZCU102 and ZCU104 Silicon on Chip(SOC) FPGA Boards.

Indian Institute of Technology Hyderabad (IN)
Openalex Percentile: Top 35%
Physical Unclonable Functions (PUFs) and Hardware Security
0.49
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