Lockstep Vs Microarchitecture: A Comparison

Safety/mission-critical applications require high dependability of the control systems. Their state-of-the-art protection approach is a system-level lockstep. This paper compares the system-level dual and triple lockstep technique to the microarchitecture-level protection of the Hardisc RISC-V core. For a fair comparison, each system is based on the same core(s) and integrates protection against bit-flips in memory and transient faults in the bus. We propose a fault injection methodology, combining pre-synthesis simulation with synthesis data to analyse the vulnerability of a system to faults. The fault injection campaigns show that the Hardisc can withstand fault rates orders of magnitude higher than the dual-core lockstep system while preserving the same area and power consumption. It comes with a 5% frequency penalty. We have shown that system failures are more frequent once the fault rate reaches an application-specific threshold (one fault in 100 clock cycles).