16-Bit SABP: Quasi-Stochastic Data Representation Unit for AI Hardware Using FPGA

Efficient data representation is a cornerstone in various domains such as Artificial Intelligence (AI), image processing, and video processing. Discovering the optimal data representation is key to enhancing interfacing, reducing computational complexity, and minimizing power consumption, particularly for digital hardware platforms. This paper presents three modifications to the state-of-the-art 10-bit Bent-Pyramid system, known for its quasi-stochastic data representation. We propose an upgrade to a 16-bit Bent Pyramid (BP), aiming to achieve a higher dynamic range resolution. These proposed three phases are the 16-bit Bent Pyramid (BP), the 16-bit Shifted Bent Pyramid (SBP), and the 16-bit Shifted Asserted Bent Pyramid (SABP). Throughout these modification stages, the latest version of BSA-BP effectively decreases the maximum multiplication error to an impressive $8.2 \%$ in a single multiplication instance, as opposed to $9 \%$ in two multiplication instances observed in the state-of-the-art research. The SABP architecture has been designed using VHDL, and the targeted FPGA was the Intel Cyclone V 5CGXFC9D6F27C7 chip. According to the synthesis findings of the Intel Quartus Prime software, the maximum operating frequency is 969.93 MHz, and there is only 7.02 mW of total thermal power dissipation per SABP block. The suggested 16-bit SABP demonstrated a lower maximum error rate drop of $\mathbf{8 . 8 9 \%}$ and $\mathbf{7 . 8 6 \%}$, respectively, in contrast to the cutting-edge 10bit BP and the 16-bit SC.