A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15 Gb/s for TSV Interface

In this study, a low-voltage and area-efficient through-silicon via (TSV) I/O with a quadrature error corrector (QEC) is proposed in a 65-nm CMOS process for the TSV interface in high-bandwidth memory (HBM). As data rates and the number of stacked TSVs increase, signal integrity is significantly degraded at low-voltage operation due to the following factors: insufficient timing margins in serializer and equalizer, insufficient eye-margin in TSV signaling, and clock (CK) mismatches. To ensure sufficient timing margins, a 4:1 multiplexing (MUX) output driver with an overlapped MUX (OVM) technique is adopted in the transmitter (TX). To improve eye-margin, a hybrid equalizer and direct-feedback one-tap decision feedback equalizer (DFE) are adopted in the TX and receiver (RX), respectively. CK mismatches are calibrated through the proposed QEC. A 12-stacked TSVs channel is emulated using six metal layers in the 65 nm CMOS process. The measured energy efficiency is 0.137–0.145 pJ/b/pF at 8–15 Gb/s data rates, respectively, with 0.6–0.7 V supply voltage.