Design of Concurrent Dual Band Low Noise Amplifier for WLAN Applications

This paper presents a dual band LNA CMOS designed for a Wireless Local Area Network (WLAN) application using CMOS 0.13-µm Silterra technology. The proposed design incorporates forward body bias technique with cascode and notch filter configuration to achieve both low power consumption and high gain. The simulation results demonstrate a total power consumption of 2.39 mW at a low supply voltage of 0.5 V, with a gain of 16 dB at 2.4 GHz and 12 dB at 5.2 GHz. Additionally, input return loss of -12.3 dB and -14.2 dB with noise figures of 2.93 dBm and 4.23 dBm were obtained at 2.4 GHz and 5.2 GHz, respectively. Overall, this research contributes to the development of dual band LNA designs for WLAN applications.