Design of Low Voltage & Power Digital Delay Locked Loop in 65nm CMOS Technology

A 1.4 GHz, delay locked loop (DLL) implemented and simulated in TSMC 65nm CMOS technology is demonstrated in this paper. Traditional architecture of DLL is modified to improve performance of jitter and lock time. In the proposed architecture of DLL, charge pump is eliminated to cater the problem of leakage current. The proposed system has closed loop architecture which employs an accumulator to adjust the delay line. The recommended architecture has low voltage, low power consumption and having jitter less than 1 ps. It also requires less silicon area. The demonstrated DLL locks in 18–20 input clock cycles having 210 ps locking window with rms jitter is only 0.184 ps at 1.4 GHz frequency. Our proposed DLL dissipates only 67.15 μW at 1.4 GHz frequency and the supply voltage is 1.2 V.